verification - Present State of Random Number Generator in System Verilog -

how can present state or present seed of random number generator in system verilog??

use get_randstate(), defined as

function string get_randstate(); 

from systemverilog 2012 language spec:

the get_randstate() method returns copy of internal state of rng associated given object. rng state string of unspecified length , format. length , contents of string implementation dependent.

note systemverilog create separate rng each thread , object, you'll see different results different objects.

example:

t1 = new; t2 = new; $display(t1.get_randstate()); $display(t2.get_randstate()); 

sample output incisive:

svseed=1 ; 5864a323c57f14c ;  svseed=1 ; bbfc1b9e8eb663ae ;