ModelSim VHDL real simulation time estimation -

sirs have problem resolve urgently. want vhdl simulation time of model testbench. work in modelsim , know profiler of modelsim supports performance analyzation, not information want. time consuming not means simulation steps, real time running on computer. hope give me help, maybe sentences in vhdl or commands in modelsim or other third part tools. thanks.

modelsim has tcl interpreter running, can use that.

the clock seconds function start, store value @ beginning , @ end , subtract them.

tcl tutorial starts here.

for example (caveat lector: i'm no tcl expert, , it's been long time since wrote @ :)

set start [clock seconds]      # store start time run -all                       # run simulation assuming terminates when finished! set finish [clock seconds]     # store end time puts [ expr {finish - start} ] # print out difference